1. Technical Field
The present invention relates to a semiconductor memory device, and more particularly, to an apparatus and method for controlling refresh of a semiconductor memory device comprising a Dynamic Random Memory (DRAM) memory cell and a Static Random Access Memory (SRAM) interface.
2. Description of Related Art
Generally, DRAM memory cells employ cell capacitors for storing data and cell transistors for accessing the stored data. If the cell capacitors lose their charge due to leakage current, the data is lost. Therefore, DRAM memory cells have to be periodically refreshed. Refresh is a recharging process to hold the data stored in the DRAM memory cells. The refresh operation is usually activated by an external refresh command.
SRAMs retain data bits in their memory cells as long as power is supplied. Thus, SRAMs do not need to be periodically refreshed. Memory devices having DRAM memory cells and an SRAM interface generally refresh the DRAM memory cells without responding to external refresh commands.
FIG. 1 is a timing diagram of an internal refresh operation of a conventional memory device having DRAM memory cells and an SRAM interface. A power-up sequence starts from a time when an external power voltage (EVCC) is saturated or reaches steady state, to a time when a predetermined time (for example, 200xe2x96xa1s) elapses. The power-up sequence takes a time interval (T10). During the power-up sequence (T10), the memory device does not consume current, and voltage levels of internal power voltage generating circuits (for example, various DC generating circuits) are set to target voltage levels for normal refresh operation.
A refresh oscillator (Ref. Oscillator) (not shown) is activated at a voltage lower than the full external power voltage (EVCC) at point (A), at which a power-up signal (PVCCH) is considered to be at a logic xe2x80x9chighxe2x80x9d level. In response to the activation of the power-up signal (PVCCH), the refresh oscillator (Ref. Oscillator) generates a refresh pulse (REF WL) having a predetermined cycle to sequentially refresh word lines. Therefore, data stored in the DRAM memory cells are sequentially refreshed in response to the refresh pulse (REF WL).
Since the refresh oscillator (Ref. Oscillator) is activated before the external power voltage (EVCC) completes the power-up sequence (T10), some current is consumed by the conventional memory device before the external power voltage (EVCC) completes the power-up sequence (T10). This results in increased time for setting the internal power voltage generating circuit to target levels, thereby increasing the chance of unstable operation of the internal power voltage generating circuit. Further, when the power-up signal (PVCCH) reaches (A), circuits in the memory device may be triggered and enter an unspecified state.
Thus, a need exists for an apparatus which controls a semiconductor memory device to perform refresh after the power-up sequence (T10) is completed, and to perform stable refresh without false triggering.
It is an object of the present invention to provide an apparatus and method for controlling refresh of a semiconductor memory device capable of performing an internal refresh operation after a power-up sequence is completed.
It is another object of the present invention to provide an apparatus and method for controlling refresh of a semiconductor memory device to prevent current from being consumed during the power-up sequence.
It is a further object of the present invention to provide an apparatus and method for controlling refresh of a semiconductor memory device to stably operate regardless of activation level of the power-up signal (PVCCH).
According to one aspect of the present invention, an apparatus for controlling a refresh operation of a memory device comprising DRAM memory cells and a SRAM interface, comprises a control circuit for outputting a control signal in a second state in response to a power-up signal during a predetermined period, the second state for disabling refresh operations, and for outputting the control signal in a first state in response to a command signal, wherein the command signal is a first active command input signal after the predetermined period, and a refresh pulse generating circuit for outputting a pulse signal for refreshing the DRAM memory cells in response to the control signal in the first state.
In a preferred embodiment of the present invention, a control circuit comprises a node, a first element for pulling down the node to a logic low in response to the power-up signal, a second element for pulling up the node to a logic high in response to the command signal, and a third element for inverting the logic level at the node to generate the control signal.
According to another aspect of the present invention, a memory device comprising DRAM cells, comprises a control circuit for generating a control signal in response to a data write/read command, wherein the command is the first input signal after a power-up sequence is completed, and a refresh pulse generating circuit for generating a pulse signal for refreshing the DRAM cells in response to the control signal.
According to further aspect of the present invention, a method for controlling a refresh operation of a memory device comprising DRAM memory cells and an SRAM interface, comprises outputting a control signal in a second state during a predetermined period in response to a power-up signal, outputting the control signal in a first state in response to a command signal, wherein the command signal is a first active command input signal after the predetermined period, and outputting a signal pulse for refreshing the DRAM memory cells in response to the control signal in the first state.